The TM3 PowerPC™ PMC module delivers an outstanding combination of computational and I/O peformance in a compact, industry standard form factor. On its own, or as part of a multiprocessing system, the TM3 is a powerful engine for embedded applications including DSP, imaging, computer telephony and transac tion processing. The TM3 may be specified with either a PowerPC™ G3 (750) or G4 (7400) CPU. These devices use a highly advanced superscalar architecture to deliver exceptional integer and floating point performance. They include large on-chip instruction and data caches, a fast L2 cache controller, and a 66MHz 64-bit 60x bus interface. The PowerPC G4 benefits from improved memory bandwidth and an AltiVec™ 128 bit vector processing engine which can perform 4 single precision floating point operations per clock. A 1 or 2Mbyte L2 cache is implemented using fast pipeline burst SRAMs. This is connected to the CPU by a dedicated 64-bit backside bus running at half the CPU core speed. The CPU is connected to the SDRAM memory by a proprietary controller which is

The TM3 PCI controller is a PCI 2.1 compliant initiator and target, and can generate and respond to configuration cycles. It uses byte invariant addressing and includes hardware endian-conversion. A pair of flexible DMA engines supports very high performance bus mastering.

As a target, it makes all on board resources visible to the host and other PCI initiators, including SDRAM, peripherals and control registers. Deep FIFO buffers allow burst transfers to and from SDRAM to achieve a bandwidth of 120Mbytes/sec sustained. As an initiator, it allows the CPU and DMA engines to directly access other devices. The DMA engines can move data between the TM3 and other devices at 120Mbytes/sec sustained, with full support for scatter/gather and unaligned transfers.

The TM3 includes the standard peripherals required by mainstream RTOSs: a flash ROM for boot firmware, a small NVRAM, a timer and a serial port. Utilities are supplied to test and program the flash ROM and NVRAM, as are programming examples for the timer and serial port.

For development purposes, CPU operation can be fully controlled by the host through PCI registers which provide access to reset and interrupt functions, and bootstrap code may be located in SDRAM. Alternatively, the TM3 may be configured to boot from its flash ROM without host intervention.

Additionally, the TM3 includes a JTAG TAP socket and adapter that is compatible with AMC’s PowerTAP debugger. This offers power and functionality similar to a full in-circuit emulator.

The TM3 ships with a CD-ROM packed with resources and tools, including:

• GNU C cross compiler for Win32 and Linux hosts

• host drivers, libraries and utilities for Windows NT, Linux and DOS

• comprehensive PowerPC runtime libraries with full source code

• full product documentation

To request technical literature or pricing information, please contact our sales team.