TM7-LX5 - Universal Dual Xilinx Virtex 5LX PMC

• Conforms to ANSI/VITA 39-2003 (“PCI-X for PMC and Processor PMC“), ANSI/VITA 32-2003 (“Processor PMC”) and  IEEE 1386.1 PMC (“PCI Mezzanine Card")
• Optional single or dual User Xilinx® Virtex-5 FPGA's in a range LX110-220-330 (FF1760 package)
• Xilinx® Virtex-II-1000 as System FPGA
• 64bit 66Mhz PCI implemented as IP core or custom user interface via PMC connectors
• Local Bus connection to all three FPGA
• Wide Inner Bus connecting User FPGA
• Expansion Bus for multi-module systems
• On board programmable clock
• Up to 512Mb FLASH memory for FPGA booting and BIOS implementation
• On-module DC-DC total more that 75 Watts
• MS Windows 98/2000/NT/XP and Linux software support

The TM7-LX5  is a PCI Mezzanine Card (PMC) based on Virtex-5 Field Programmable Gate Array technology (FPGA). The TM7-LX5 is an evolution of previous generation TMFXx modules. Advantages of the TM7-LX5 include new range of User FPGA and EM slots connected to them.

Included on the TM7-LX5 are three FPGA Virtex devices with the Virtex-II System FPGA used as a Control block to interface the TM7-LX5 module to the outside world. It can implement a Xilinx PCI-64/66 core or user defined interface. Serial PROM is connected to the System FPGA and is used to configure it at start up The FLASH memory also connected to System FPGA.

The System FPGA is connected to each User FPGA by a common Local Bus and separate Control Buses. The Control Buses used to configure, boot and control User FPGA.  

The User FPGAs can be booted either directly from the JTAG interface or from the Control Bus via the System FPGA - from the FLASH memory, through the PCI or user defined interface. A wide Inner Bus connects each User FPGA.

216 lines from each User FPGA are connected to external connectors (Jx). These lines can be used either as 72 pairs and 72 singles or 216 single lines and organize External Buses for off module communication.

There are special blocks on-board that allow the control of some of the FPGA and module parameters such as temperature and voltage. These are connected by I2C bus and routed off module.

The Clock manager converts the 25MHz input into four independent clocks Two are connected to the System FPGA and one to each User FPGA. The additional 200MHz differential clock with low jitter is connected to the first User FPGA only.

The high-capacity DC-DC converters allow high-powered user IP-core applications: User FPGA cores have a 1V/50A DC-DC supply and their banks have 2.5/10A DC-DC supplies.

To request technical literature or pricing information, please contact our sales team.